Embodiments of the present invention relate in general to an out-of-order (OoO) processor and more specifically to effective address based instruction fetch unit in out of order processors by removal of effective-to-real address table entries in an OoO processor.
In an OoO processor, an instruction sequencing unit (ISU) dispatches instructions to various issue queues, renames registers in support of OoO execution, issues instructions from the various issue queues to the execution pipelines, completes executed instructions, and handles exception conditions. Register renaming is typically performed by mapper logic in the ISU before the instructions are placed in their respective issue queues. The ISU includes one or more issue queues that contain dependency matrices for tracking dependencies between instructions. A dependency matrix typically includes one row and one column for each instruction in the issue queue.
In the OoO processor, a level one cache (L1) instruction cache is often incorporated on the processor chip. The L1 is intended to hold instructions considered likely to be executed in the immediate future. The L1 instruction cache complex includes an effective-to-real address table (ERAT), which functions as a cache of the address translation table for main memory. The ERAT contains pairs of effective and corresponding real address portions. ERAT entries are accessed with a hash function of the effective address of a desired instruction. The effective address portion in the ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real address portion is compared with a portion of real address in a directory array to verify a cache hit.